Cell current control through power supply

ABSTRACT

Techniques and corresponding circuitry are presented for controlling the amount of current flowing through the cells of a memory circuit during a sensing operation though a feedback arrangement. The amount of current supplied to bit lines from an external power supply by regulation circuitry is compared with a reference level. Based on this comparison, the level on the control gates of clamp transistors in the sense amp circuits is set to control the amount of current supplied to the bit lines. This can reduce device variation since the levels are replicated locally at the generator on the chip. The circuitry can also be used more generally to determine the current level drawn during a sensing operation.

FIELD OF THE INVENTION

This invention relates generally to non-volatile semiconductor memory such as electrically erasable programmable read-only memory (EEPROM) and flash EEPROM, and specifically to sensing circuits for such memories.

BACKGROUND OF THE INVENTION

Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as a small form factor card, has become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Unlike RAM (random access memory) that is also solid-state memory, flash memory is non-volatile and retains its stored data even after power is turned off. In spite of the higher cost, flash memory is increasingly being used in mass storage applications. Conventional mass storage, based on rotating magnetic medium such as hard drives and floppy disks, is unsuitable for the mobile and handheld environment. This is because disk drives tend to be bulky, are prone to mechanical failure and have high latency and high power requirements. These undesirable attributes make disk-based storage impractical in most mobile and portable applications. On the other hand, flash memory, both embedded and in the form of a removable card, are ideally suited in the mobile and handheld environment because of its small size, low power consumption, high speed and high reliability features.

EEPROM and electrically programmable read-only memory (EPROM) are non-volatile memory that can be erased and have new data written or “programmed” into their memory cells. Both utilize a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions.

The floating gate can hold a range of charges and therefore can be programmed to any threshold voltage level within a threshold voltage window (also referred to as a “conduction window”). The size of the threshold voltage window is delimited by the minimum and maximum threshold levels of the device, which in turn correspond to the range of the charges that can be programmed onto the floating gate. The threshold window generally depends on the memory device's characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level range within the window may, in principle, be used to designate a definite memory state of the cell. When the threshold voltage is partitioned into two distinct regions, each memory cell will be able to store one bit of data. Similarly, when the threshold voltage window is partitioned into more than two distinct regions, each memory cell will be able to store more than one bit of data.

In a two-state EEPROM cell, at least one current breakpoint level is established so as to partition the conduction window into two regions. When a cell is read by applying predetermined, fixed voltages, its source/drain current is resolved into a memory state by comparing with the breakpoint level (or reference current IREF). If the current read is higher than that of the breakpoint level, the cell is determined to be in one logical state (e.g., a “zero” state). On the other hand, if the current is less than that of the breakpoint level, the cell is determined to be in the other logical state (e.g., a “one” state). Thus, such a two-state cell stores one bit of digital information. A reference current source, which may be externally programmable, is often provided as part of a memory system to generate the breakpoint level current.

In order to increase memory capacity, flash EEPROM devices are being fabricated with higher and higher density as the state of the semiconductor technology advances. Another method for increasing storage capacity is to have each memory cell store more than two states.

For a multi-state or multi-level EEPROM memory cell, the conduction window is partitioned into more than two regions by more than one breakpoint such that each cell is capable of storing more than one bit of data. The information that a given EEPROM array can store is thus increased with the number of states that each cell can store. EEPROM or flash EEPROM with multi-state or multi-level memory cells have been described in U.S. Pat. No. 5,172,338.

The transistor serving as a memory cell is typically programmed to a “programmed” state by one of two mechanisms. In “hot electron injection,” a high voltage applied to the drain accelerates electrons across the substrate channel region. At the same time a high voltage applied to the control gate pulls the hot electrons through a thin gate dielectric onto the floating gate. In “tunneling injection,” a high voltage is applied to the control gate relative to the substrate. In this way, electrons are pulled from the substrate to the intervening floating gate.

The memory device may be erased by a number of mechanisms. For EPROM, the memory is bulk erasable by removing the charge from the floating gate by ultraviolet radiation. For EEPROM, a memory cell is electrically erasable, by applying a high voltage to the substrate relative to the control gate so as to induce electrons in the floating gate to tunnel through a thin oxide to the substrate channel region (i.e., Fowler-Nordheim tunneling.) Typically, the EEPROM is erasable byte by byte. For flash EEPROM, the memory is electrically erasable either all at once or one or more blocks at a time, where a block may consist of 512 bytes or more of memory.

The memory devices typically comprise one or more memory chips that may be mounted on a card. Each memory chip comprises an array of memory cells supported by peripheral circuits such as decoders and erase, write and read circuits. The more sophisticated memory devices operate with an external memory controller that performs intelligent and higher level memory operations and interfacing.

There are many commercially successful non-volatile solid-state memory devices being used today. These memory devices may be flash EEPROM or may employ other types of nonvolatile memory cells. Examples of flash memory and systems and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, and 5,661,053, 5,313,421 and 6,222,762. In particular, flash memory devices with NAND string structures are described in U.S. Pat. Nos. 5,570,315, 5,903,495, 6,046,935.

Nonvolatile memory devices are also manufactured from memory cells with a dielectric layer for storing charge. Instead of the conductive floating gate elements described earlier, a dielectric layer is used. Such memory devices utilizing dielectric storage element have been described by Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11, November 2000, pp. 543-545. An ONO dielectric layer extends across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. For example, U.S. Pat. Nos. 5,768,192 and 6,011,725 disclose a nonvolatile memory cell having a trapping dielectric sandwiched between two silicon dioxide layers. Multi-state data storage is implemented by separately reading the binary states of the spatially separated charge storage regions within the dielectric.

Programming a page of memory cells typically involves a series of alternating program/verify cycles. Each program cycle has the page of memory cells subject to one or more programming voltage pulses. The program cycle is followed by a verify cycle in which each cell is read back to determine if it has been programmed correctly. Those cells that have been verified will be program-inhibited from subsequent programming pulses. The program/verify cycles continue with increasing programming voltage level until all cells in the page have been program-verified.

Both reading and verifying operations are performed by executing one or more sensing cycle in which the conduction current or threshold voltage of each memory cell of the page is determined relative to a demarcation value. In general, if the memory is partitioned into n states, there will be at least n−1 sensing cycles to resolve all possible memory states. In many implementations each sensing cycle may also involve two or more passes. For example, when the memory cells are closely packed, interactions between neighboring charge storage elements become significant and some sensing techniques involve sensing memory cells on neighboring word lines in order to compensate for errors caused by these interactions.

In order to improve read and program performance, multiple charge storage elements or memory transistors in an array are read or programmed in parallel. Thus, a “page” of memory elements are read or programmed together. In existing memory architectures, a row typically contains several interleaved pages or it may constitute one page of contiguous memory cells. All memory elements of a page will be read or programmed together. In currently produced semiconducting integrated circuit memory chips, a memory page may have as many as 64,000 memory cells or memory elements being read or sensed in parallel.

There is an ongoing need for increased performance and more efficient device operation. The massively parallel memory page presents significant issues of current and power consumption. Therefore there is a general need for high capacity, high performance non-volatile memory that uses less current.

SUMMARY OF INVENTION

In a first set of aspects, a non-volatile memory circuit includes an array of non-volatile memory cells and a plurality of bit lines connectable to the memory cells. The memory circuit also includes regulation circuitry connectable to receive an external power supply level and provide therefrom a regulated voltage level, a plurality of sense amps, and current control circuitry. Each of the sense amps has a clamp transistor through which the regulated voltage level is connectable to supply a selected bit line. The current control circuitry is connected to the regulation circuitry to perform a comparison of the amount of current supplied by the regulation circuitry to the bit lines with a reference level and connected to the control gates of the clamp transistors to supply a clamp voltage thereto based upon said comparison.

According to other aspects, a non-volatile memory circuit includes an array of non-volatile memory cells and a plurality of bit lines connectable to the memory cells. The memory circuit also includes regulation circuitry connectable to receive an external power supply level and provide therefrom a regulated voltage level, intermediate circuitry through which the regulated voltage level is connectable to supply a plurality of selected bit lines, and current determination circuitry. The current determination circuitry is connected to the regulation circuitry to perform a comparison of the amount of current supplied by the regulation circuitry to the bit lines with a reference level. The current determination circuitry includes a first transistor and a reference current source connected in series between the external power supply level and ground. The gate of the first transistor is connected to the regulation circuitry to receive a voltage indicative of the amount of current supplied by the regulation circuitry to the bit lines. The current determination circuitry also includes and a comparator having a first input connected to the a node between the first transistor and the reference current source, having a second input connected to a reference level, and providing an output indicative of the amount of current being supplied to the selected bit lines by the regulation circuitry.

Various aspects, advantages, features and embodiments of the present invention are included in the following description of exemplary examples thereof, which description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of terms between any of the incorporated publications, documents or things and the present application, those of the present application shall prevail.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates schematically the functional blocks of a non-volatile memory chip in which the present invention may be implemented.

FIG. 2 illustrates schematically a non-volatile memory cell.

FIG. 3 illustrates the relation between the source-drain current I_(D) and the control gate voltage V_(CG) for four different charges Q1-Q4 that the floating gate may be selectively storing at any one time.

FIG. 4 illustrates an example of an NOR array of memory cells.

FIG. 5A illustrates schematically a string of memory cells organized into an NAND string.

FIG. 5B illustrates an example of an NAND array of memory cells, constituted from NAND strings such as that shown in FIG. 5A.

FIG. 6 illustrates a typical technique for programming a page of memory cells to a target memory state by a series of alternating program/verify cycles.

FIG. 7(1) illustrates the threshold voltage distributions of an example 4-state memory array with an erased state as a ground state “Gr” and progressively more programmed memory states “A”, “B” and “C”.

FIG. 7(2) illustrates a preferred, 2-bit LM coding to represent the four possible memory states shown in FIG. 7(1).

FIG. 8(1) illustrates the threshold voltage distributions of an example 8-state memory array.

FIG. 8(2) illustrates a preferred, 3-bit LM coding to represent the eight possible memory states shown in FIG. 8(1).

FIG. 9 illustrates the Read/Write Circuits, shown in FIG. 1, containing a bank of sense modules across an array of memory cells.

FIG. 10 illustrates schematically a preferred organization of the sense modules shown in FIG. 9.

FIG. 11 illustrates in more detail the read/write stacks shown in FIG. 10.

FIG. 12 illustrates schematically an exemplary embodiment for sense amplifier circuit.

FIG. 13 illustrates an example of a sensing operation using the circuit of FIG. 12.

FIG. 14 illustrates an example of a lockout sensing operation using the circuit of FIG. 12.

FIG. 15 illustrates an example of a quick pass write operation with two forced values using the circuit of FIG. 12.

FIG. 16 illustrates an example of a quick pass write operation with three forced values using the circuit of FIG. 12.

FIG. 17 illustrates an example of a floating quick pass write operation using the circuit of FIG. 12.

FIG. 18 illustrates an example of measuring cell current using an external bias voltage using the circuit of FIG. 12.

FIG. 19 illustrates schematically a second exemplary embodiment for sense amplifier circuit.

FIGS. 20A and 20B are respective waveforms for a binary program operation for the circuits of FIGS. 12 and 19.

FIGS. 21A and 21B are respective waveforms for a binary program verify operation for the circuits of FIGS. 12 and 19.

FIGS. 22A and 22B are respective waveforms for a multi-state program verify operation for the circuits of FIGS. 12 and 19.

FIG. 23 illustrates schematically a third exemplary embodiment for sense amplifier circuit.

FIG. 24 illustrates schematically a third exemplary embodiment for sense amplifier circuit.

FIGS. 25A and 25B illustrate some waveforms for different ways of implementing a verify operation in quick pass write.

FIG. 26 shows the variation of cell current levels as a device ages and at differing clamp voltages.

FIG. 27 illustrates an exemplary embodiment for circuitry to control cell current.

FIG. 28 gives more detail for the embodiment of FIG. 27.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Memory System

FIG. 1 to FIG. 11 illustrate example memory systems in which the various aspects of the present invention may be implemented.

FIG. 1 illustrates schematically the functional blocks of a non-volatile memory chip in which the present invention may be implemented. The memory chip 100 includes a two-dimensional array of memory cells 200, control circuitry 210, and peripheral circuits such as decoders, read/write circuits and multiplexers.

The memory array 200 is addressable by word lines via row decoders 230 (split into 230A, 230B) and by bit lines via column decoders 260 (split into 260A, 260B) (see also FIGS. 4 and 5.) The read/write circuits 270 (split into 270A, 270B) allow a page of memory cells to be read or programmed in parallel. A data I/O bus 231 is coupled to the read/write circuits 270.

In a preferred embodiment, a page is constituted from a contiguous row of memory cells sharing the same word line. In another embodiment, where a row of memory cells are partitioned into multiple pages, block multiplexers 250 (split into 250A and 250B) are provided to multiplex the read/write circuits 270 to the individual pages. For example, two pages, respectively formed by odd and even columns of memory cells are multiplexed to the read/write circuits.

FIG. 1 illustrates a preferred arrangement in which access to the memory array 200 by the various peripheral circuits is implemented in a symmetric fashion, on opposite sides of the array so that the densities of access lines and circuitry on each side are reduced in half. Thus, the row decoder is split into row decoders 230A and 230B and the column decoder into column decoders 260A and 260B. In the embodiment where a row of memory cells are partitioned into multiple pages, the page multiplexer 250 is split into page multiplexers 250A and 250B. Similarly, the read/write circuits 270 are split into read/write circuits 270A connecting to bit lines from the bottom and read/write circuits 270B connecting to bit lines from the top of the array 200. In this way, the density of the read/write modules, and therefore that of the sense modules 380, is essentially reduced by one half.

The control circuitry 110 is an on-chip controller that cooperates with the read/write circuits 270 to perform memory operations on the memory array 200. The control circuitry 110 typically includes a state machine 112 and other circuits such as an on-chip address decoder and a power control module (not shown explicitly). The state machine 112 provides chip level control of memory operations. The control circuitry is in communication with a host via an external memory controller.

The memory array 200 can be organized as a two or three dimensional array of memory cells arranged in rows and columns and addressable by word lines and bit lines. Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.

The memory devices can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse, phase change material, etc., and optionally a steering element, such as a diode, etc. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.

Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are exemplary, and memory elements may be otherwise configured.

The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two dimensional memory structure or a three dimensional memory structure.

In a two dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-z direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.

The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.

A three dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate).

As a non-limiting example, a three dimensional memory structure may be vertically arranged as a stack of multiple two dimensional memory device levels. As another non-limiting example, a three dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements in each column. The columns may be arranged in a two dimensional configuration, e.g., in an x-z plane, resulting in a three dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three dimensional memory array.

By way of non-limiting example, in a three dimensional NAND memory array, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., x-z) memory device levels. Alternatively, the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels. Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels. Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.

Typically, in a monolithic three dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three dimensional memory array may be shared or have intervening layers between memory device levels. More detail and examples of three dimensional memory structures can be found in U.S. patent application Ser. Nos. 14/328,018; 14/328,021; 14/328,027; 14/328,037; and 14/328,0070, all of which were filed on Jul. 10, 2014; and Ser. No. 14/456,853, that was filed on Aug. 11, 2014.

Then again, two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple layers of memory. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. The substrates may be thinned or removed from the memory device levels before stacking, but as the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three dimensional memory arrays. Further, multiple two dimensional memory arrays or three dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked-chip memory device.

Associated circuitry is typically required for operation of the memory elements and for communication with the memory elements. As non-limiting examples, memory devices may have circuitry used for controlling and driving memory elements to accomplish functions such as programming and reading.

FIG. 2 illustrates schematically an example of a non-volatile memory cell. The memory cell 10 can be implemented by a field-effect transistor having a charge storage unit 20, such as a floating gate or a dielectric layer. The memory cell 10 also includes a source 14, a drain 16, and a control gate 30.

There are many commercially successful non-volatile solid-state memory devices being used today. These memory devices may employ different types of memory cells, each type having one or more charge storage element.

Typical non-volatile memory cells include EEPROM and flash EEPROM. Examples of EEPROM cells and methods of manufacturing them are given in U.S. Pat. No. 5,595,924. Examples of flash EEPROM cells, their uses in memory systems and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, 5,661,053, 5,313,421 and 6,222,762. In particular, examples of memory devices with NAND cell structures are described in U.S. Pat. Nos. 5,570,315, 5,903,495, 6,046,935. Also, examples of memory devices utilizing dielectric storage element have been described by Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11, November 2000, pp. 543-545, and in U.S. Pat. Nos. 5,768,192 and 6,011,725.

In practice, the memory state of a cell is usually read by sensing the conduction current across the source and drain electrodes of the cell when a reference voltage is applied to the control gate. Thus, for each given charge on the floating gate of a cell, a corresponding conduction current with respect to a fixed reference control gate voltage may be detected. Similarly, the range of charge programmable onto the floating gate defines a corresponding threshold voltage window or a corresponding conduction current window.

Alternatively, instead of detecting the conduction current among a partitioned current window, it is possible to set the threshold voltage for a given memory state under test at the control gate and detect if the conduction current is lower or higher than a threshold current. In one implementation the detection of the conduction current relative to a threshold current is accomplished by examining the rate the conduction current is discharging through the capacitance of the bit line.

FIG. 3 illustrates the relation between the source-drain current I_(D) and the control gate voltage V_(CG) for four different charges Q1-Q4 that the floating gate may be selectively storing at any one time. The four solid I_(D) versus V_(CG) curves represent four possible charge levels that can be programmed on a floating gate of a memory cell, respectively corresponding to four possible memory states. As an example, the threshold voltage window of a population of cells may range from 0.5V to 3.5V. Eight possible memory states “0”, “1”, “2”, “3”, “4”, “5”, “6” and “7” respectively representing one erased and seven programmed states, may be demarcated by partitioning the threshold window into eight regions in interval of about 0.4V each. For example, if a reference current, TREF of 0.05 uA is used as shown, then the cell programmed with Q1 may be considered to be in a memory state “1” since its curve intersects with I_(REF) in the region of the threshold window demarcated by VCG=0.43V and 0.88V. Similarly, Q4 is in a memory state “5”.

As can be seen from the description above, the more states a memory cell is made to store, the more finely divided is its threshold window. For example, a memory device may have memory cells having a threshold window that ranges from −1.5V to 5V. This provides a maximum width of 6.5V. If the memory cell is to store 16 states, each state may occupy from 350 mV to 450 mV in the threshold window. This will require higher precision in programming and reading operations in order to be able to achieve the required resolution.

FIG. 4 illustrates an example of an NOR array of memory cells. In the memory array 200, each row of memory cells are connected by their sources 14 and drains 16 in a daisy-chain manner. This design is sometimes referred to as a virtual ground design. The cells 10 in a row have their control gates 30 connected to a word line, such as word line 42. The cells in a column have their sources and drains respectively connected to selected bit lines, such as bit lines 34 and 36.

FIG. 5A illustrates schematically a string of memory cells organized into an NAND string. An NAND string 50 comprises of a series of memory transistors M1, M2, . . . Mn (e.g., n=4, 8, 16 or higher) daisy-chained by their sources and drains. A pair of select transistors S1, S2 controls the memory transistors chain's connection to the external via the NAND string's source terminal 54 and drain terminal 56 respectively. In a memory array, when the source select transistor S1 is turned on, the source terminal is coupled to a source line (see FIG. 5B). Similarly, when the drain select transistor S2 is turned on, the drain terminal of the NAND string is coupled to a bit line of the memory array. Each memory transistor 10 in the chain acts as a memory cell. It has a charge storage element 20 to store a given amount of charge so as to represent an intended memory state. A control gate 30 of each memory transistor allows control over read and write operations. As will be seen in FIG. 5B, the control gates 30 of corresponding memory transistors of a row of NAND string are all connected to the same word line. Similarly, a control gate 32 of each of the select transistors S1, S2 provides control access to the NAND string via its source terminal 54 and drain terminal 56 respectively. Likewise, the control gates 32 of corresponding select transistors of a row of NAND string are all connected to the same select line.

When an addressed memory transistor 10 within an NAND string is read or is verified during programming, its control gate 30 is supplied with an appropriate voltage. At the same time, the rest of the non-addressed memory transistors in the NAND string 50 are fully turned on by application of sufficient voltage on their control gates. In this way, a conductive path is effective created from the source of the individual memory transistor to the source terminal 54 of the NAND string and likewise for the drain of the individual memory transistor to the drain terminal 56 of the cell. Memory devices with such NAND string structures are described in U.S. Pat. Nos. 5,570,315, 5,903,495, 6,046,935.

FIG. 5B illustrates an example of an NAND array 200 of memory cells, constituted from NAND strings 50 such as that shown in FIG. 5A. Along each column of NAND strings, a bit line such as bit line 36 is coupled to the drain terminal 56 of each NAND string. Along each bank of NAND strings, a source line such as source line 34 is coupled to the source terminals 54 of each NAND string. Also the control gates along a row of memory cells in a bank of NAND strings are connected to a word line such as word line 42. The control gates along a row of select transistors in a bank of NAND strings are connected to a select line such as select line 44. An entire row of memory cells in a bank of NAND strings can be addressed by appropriate voltages on the word lines and select lines of the bank of NAND strings. When a memory transistor within a NAND string is being read, the remaining memory transistors in the string are turned on hard via their associated word lines so that the current flowing through the string is essentially dependent upon the level of charge stored in the cell being read.

Program and Verify

FIG. 6 illustrates a typical technique for programming a page of memory cells to a target memory state by a series of alternating program/verify cycles. A programming voltage V_(PGM) is applied to the control gate of the memory cell via a coupled word line. The V_(PGM) is a series of programming voltage pulses in the form of a staircase waveform starting from an initial voltage level, V_(PGM0). The cell under programming is subject to this series of programming voltage pulses, with an attempt each time to add incremental charges to the floating gate. In between programming pulses, the cell is read back or verified to determine its source-drain current relative to a breakpoint level. The read back process may involve one or more sensing operation. Programming stops for the cell when it has been verified to reach the target state. The programming pulse train used may have increasing period or amplitude in order to counteract the accumulating electrons programmed into the charge storage unit of the memory cell. Programming circuits generally apply a series of programming pulses to a selected word line. In this way, a page of memory cells whose control gates are coupled to the word line can be programmed together. Whenever a memory cell of the page has been programmed to its target state, it is program-inhibited while the other cells continue to be subject to programming until all cells of the page have been program-verified.

Examples of Memory State Partitioning

FIG. 7(1) illustrates the threshold voltage distributions of an example 4-state memory array with an erased state as a ground state “Gr” and progressively more programmed memory states “A”, “B” and “C”. During read, the four states are demarcated by three demarcation breakpoints, D_(A)-D_(C).

FIG. 7(2) illustrates a preferred, 2-bit LM coding to represent the four possible memory states shown in FIG. 7(1). Each of the memory states (viz., “Or”, “A”, “B” and “C”) is represented by a pair of “upper, lower” code bits, namely “11”, “01”, “00” and “10” respectively. The “LM” code has been disclosed in U.S. Pat. No. 6,657,891 and is advantageous in reducing the field-effect coupling between adjacent floating gates by avoiding program operations that require a large change in charges. The coding is designed such that the 2 code bits, “lower” and “upper” bits, may be programmed and read separately. When programming the lower bit, the threshold level of the cell either remains in the “erased” region or is moved to a “lower middle” region of the threshold window. When programming the upper bit, the threshold level of a cell in either of these two regions is further advanced to a slightly higher level in a “lower intermediate” region of the threshold window.

FIG. 8(1) illustrates the threshold voltage distributions of an example 8-state memory array. The possible threshold voltages of each memory cell spans a threshold window which is partitioned into eight regions to demarcate eight possible memory states, “Gr”, “A”, “B”, “C”, “D”, “E”, “F” and “G”. “Gr” is a ground state, which is an erased state within a tightened distribution and “A”-“G” are seven progressively programmed states. During read, the eight states are demarcated by seven demarcation breakpoints, D_(A)-D_(G).

FIG. 8(2) illustrates a preferred, 3-bit LM coding to represent the eight possible memory states shown in FIG. 8(1). Each of the eight memory states is represented by a triplet of “upper, middle, lower” bits, namely “111”, “011”, “001”, “101”, “100”, “000”, “010” and “110” respectively. The coding is designed such that the 3 code bits, “lower”, “middle” and “upper” bits, may be programmed and read separately. Thus, the first round, lower page programming has a cell remain in the “erased” or “Gr” state if the lower bit is “1” or programmed to a “lower intermediate” state if the lower bit is “0”. Basically, the “Gr” or “ground” state is the “erased” state with a tightened distribution by having the deeply erased states programmed to within a narrow range of threshold values. The “lower intermediate” states may have a broad distribution of threshold voltages that straddling between memory states “B” and “D”. During programming, the “lower intermediate” state can be verified relative to a coarse breakpoint threshold level such as D_(B). When programming the middle bit, the threshold level of a cell will start from one of the two regions resulted from the lower page programming and move to one of four possible regions. When programming the upper bit, the threshold level of a cell will start from one of the four possible regions resulted from the middle page programming and move to one of eight possible memory states.

Sensing Circuits and Techniques

FIG. 9 illustrates the Read/Write Circuits 270A and 270B, shown in FIG. 1, containing a bank of p sense modules across an array of memory cells. The entire bank of p sense modules 480 operating in parallel allows a block (or page) of p cells 10 along a row to be read or programmed in parallel. Essentially, sense module 1 will sense a current I₁ in cell 1, sense module 2 will sense a current I₂ in cell 2, . . . , sense module p will sense a current I_(p) in cell p, etc. The total cell current i_(TOT) for the page flowing out of the source line 34 into an aggregate node CLSRC and from there to ground will be a summation of all the currents in the p cells. In conventional memory architecture, a row of memory cells with a common word line forms two or more pages, where the memory cells in a page are read and programmed in parallel. In the case of a row with two pages, one page is accessed by even bit lines and the other page is accessed by odd bit lines. A page of sensing circuits is coupled to either the even bit lines or to the odd bit lines at any one time. In that case, page multiplexers 250A and 250B are provided to multiplex the read/write circuits 270A and 270B respectively to the individual pages.

In currently produced chips based on 56 nm technology p>64000 and in the 43 nm 32 Gbit x4 chip p>150000. In the preferred embodiment, the block is a run of the entire row of cells. This is the so-called “all bit-line” architecture in which the page is constituted from a row of contiguous memory cells coupled respectively to contiguous bit lines. In another embodiment, the block is a subset of cells in the row. For example, the subset of cells could be one half of the entire row or one quarter of the entire row. The subset of cells could be a run of contiguous cells or one every other cell, or one every predetermined number of cells. Each sense module is coupled to a memory cell via a bit line and includes a sense amplifier for sensing the conduction current of a memory cell. In general, if the Read/Write Circuits are distributed on opposite sides of the memory array the bank of p sense modules will be distributed between the two sets of Read/Write Circuits 270A and 270B.

FIG. 10 illustrates schematically a preferred organization of the sense modules shown in FIG. 9. The read/write circuits 270A and 270B containing p sense modules are grouped into a bank of read/write stacks 400.

FIG. 11 illustrates in more detail the read/write stacks shown in FIG. 10. Each read/write stack 400 operates on a group of k bit lines in parallel. If a page has p=r*k bit lines, there will be r read/write stacks, 400-1, . . . , 400-r. Essentially, the architecture is such that each stack of k sense modules is serviced by a common processor 500 in order to save space. The common processor 500 computes updated data to be stored in the latches located at the sense modules 480 and at the data latches 430 based on the current values in those latches and on controls from the state machine 112. Detailed description of the common processor has been disclosed in U.S. Patent Application Publication Number: US-2006-0140007-A1 on Jun. 29, 2006, the entire disclosure of which is incorporated herein by reference.

The entire bank of partitioned read/write stacks 400 operating in parallel allows a block (or page) of p cells along a row to be read or programmed in parallel. Thus, there will be p read/write modules for the entire row of cells. As each stack is serving k memory cells, the total number of read/write stacks in the bank is therefore given by r=p/k. For example, if r is the number of stacks in the bank, then p=r*k. One example memory array may have p=150000, k=8, and therefore r=18750.

Each read/write stack, such as 400-1, essentially contains a stack of sense modules 480-1 to 480-k servicing a segment of k memory cells in parallel. The page controller 410 provides control and timing signals to the read/write circuit 370 via lines 411. The page controller is itself dependent on the memory controller 310 via lines 311. Communication among each read/write stack 400 is effected by an interconnecting stack bus 431 and controlled by the page controller 410. Control lines 411 provide control and clock signals from the page controller 410 to the components of the read/write stacks 400-1.

In the preferred arrangement, the stack bus is partitioned into a SABus 422 for communication between the common processor 500 and the stack of sense modules 480, and a DBus 423 for communication between the processor and the stack of data latches 430.

The stack of data latches 430 comprises of data latches 430-1 to 430-k, one for each memory cell associated with the stack The I/O module 440 enables the data latches to exchange data with the external via an I/O bus 231.

The common processor also includes an output 507 for output of a status signal indicating a status of the memory operation, such as an error condition. The status signal is used to drive the gate of an n-transistor 550 that is tied to a FLAG BUS 509 in a Wired-Or configuration. The FLAG BUS is preferably pre-charged by the controller 310 and will be pulled down when a status signal is asserted by any of the read/write stacks.

With respect to the sense modules 480, a number of arrangements are possible, with the next section presenting one particular set of embodiments in detail. In addition, various embodiments for sense modules that can be profitably incorporated into the arrangements given above are developed in U.S. Pat. Nos. 7,593,265 and 7,957,197. Reference is also made to U.S. Pat. No. 7,046,568, which discloses a non-volatile memory device with low noise sensing circuits capable of operating at a low supply voltage; U.S. Pat. No. 7,173,854, which discloses a method of referencing the word line voltage close to the source of each memory cell in a page so as to alleviate the problem of source bias error due to the ground loop; and U.S. Pat. No. 7,447,079, which discloses a memory device and method for regulating the source of each memory cell along a page to a predetermined page source voltage.

Compact Sense Amplifiers

This section considers a particular arrangement for the sense modules 480-i for use in the read/write circuitry presented in the preceding sections. FIG. 12 is a representation of such a compact and versatile sense amp, with various aspects of its operation being illustrated with respect to FIGS. 13-18. As will be discussed, among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. (For more discussion of the quick pass write concept, see U.S. Pat. No. 7,345,928.) Also, it can provide a convenient way to measure the cell current.

Considering FIG. 12 in more detail, this shows the sense amp circuit which can be connected to a bit line at BL (lower left, below the bit line selection switch BLS 623) and to bus at SBUS (to the left of SEL 609 below the element FLAG 601). The input signal CLK is received (lower middle) can be supplied at the lower plate of the capacitor CSA 631. The sense amplifier is then also connected to a high voltage supply level (VDDSA) and ground.

A latch circuit FLAG 601 has a first leg with node FLG and a second leg with node INV, where these legs each have their node cross-coupled to the gates of a pair of series connected transistors in the other leg. The first and second legs also each include a switch formed by a PMOS respectively controlled by STF for 603 and FRB for 605, whereby each the legs can by such off above the node. The level on the node FLG can then be connected to the bus at SBUS through the switch 609 with control signal SEL. The latch can be reset through the signal RST at 607, allow INV to be set to ground.

The bit line BL can be selectively connected to the node COM by use of the bit line selection switch BLS 623 and bit line clamp BLC 621. The node COM can also be directly connected to the high supply level by the switch BLX 625. In between the bit line selection circuitry and the latch FLAG 601 is the intermediate circuitry of the sense amp. In addition to the node COM is a node MUX that is connectable to the COM node by use of the switch BLY 627. The node MUX can also be connected to the high supply level by use of the PMOS 615 controller by FLA, dependent upon the level on FLG as this is connected to the gate of PMOS 613 connected in series with FLA 615 between MUX and VDDSA.

The internal node SEN can be connected to, or isolated from, the MUX node by the H00 device 639 and the COM node by the XX0 device 633. The top place of the capacitor CSA 631 is also connected to the internal SEN node of the sense amp. In addition to being connected to the bottom plate of CSA 631, the CLK signal is also connected to the MUX node by way of the transistor 635, whose gate is connected to the SEN node, connected in series with the independently controllable device STRO 637. The switch FCO 611 allows the node MUX to be connected to, or isolated from, the level on the FLG node of the latch 601.

The arrangement of the elements in FIG. 12 has a number of useful properties, including the ability to pre-charge a bit line concurrently with a data transfer. During the bit line pre-charge through the bit line select switches, the MUX node needs to stay at the power supply voltage level. During data scanning (or called data transfer), the data information from the FLG node needs to be sent to the SBUS node. Consequently, the SBUS node toggles. Because the device FCO 611 can isolate the MUX node from the SBUS node, the MUX node will not be disturbed during the data transfer. In this way, a bit line can be pre-charged at the same time as data transfer happens. Hence, the memory circuit's performance can be improved by being able to do both of these operations at the same time.

Another useful property of the arrangement of FIG. 12 is that it allows for the three bit line values (allow, inhibit, partial inhibit) of the quick pass write (QPW) to be forced using a dynamic latch arrangement. During such a “3 BL QPW”, for the inhibited bit line case the MUX node can be firmly held at a VDDSA level during the scanning in operation. The arrangement of switches prevents the SEN node from leaking, so the SEN node's voltage can be maintained. The CLK node supplies voltage to the inhibited bit lines. The SEN node of the inhibited bit line pre-charges to a high level, passing the CLK voltage level to the inhibited BL through the CLK-SEN-STRO-BLY-BLC-BLS path.

The arrangement of FIG. 12 also allows for an easy cell current measurement. A selected bit line's voltage can be supplied from an external pad of the chip through the SBUS-SEL-FLG-FCO-MUX-BLY-COM-BLC-BLS path. This means that the corresponding FLG node needs to be at an analog voltage level: besides turning off the STF device, the INV node is pulled down to the ground by the RST device. Biasing the RST node at a logic high level can pull and hold the INV node at ground.

Some of the different modes of operation for the sense amp of FIG. 12 are discussed with reference to FIGS. 13-18.

No-Lockout Read/Program Verify Operation

As a first example, a no-lockout read or program verify mode of operation is illustrated with respect to FIG. 13. Initially, as illustrated by (1), the H00 639 and FCO 611 devices are turned on, discharging the SEN node through the FLG node as FLG is initially at ground. The bit line then pre-charges through the BLS 623-BLC 621-BLX 625 devices, as shown by (2). Next, as shown at (3), the SEN node pre-charges to a certain voltage level through the H00 639 and FLA 615 devices. The level at CLK then raises up and the XX0 633 device is then turned on, (4). The SEN node will then develop: If the memory cell is conductive, the SEN node will be discharged; otherwise the SEN node will not discharge much.

After the SEN node develops, the device pulls down the CLK node to ground. Next, the FRB 605 device is turned off, and the RST 607 device is turned on (at (6)) to reset the FLG node to the high VDDSA voltage level. Then the FRB 605 device is turned on and the RST 607 device is turned off. Subsequently, the FCO 611 device is turned on to pre-charge the MUX node from the FLG node. Next, the memory turns off the STF 603 device, then turns on the STRO 637 device to develop the FLG node, as shown at (8). The level previously at SEN will determine whether device 635 is on or not, in turn determining what level will develop on the FLG node. Once the FLG node finishes developing, the STRO 637 device is turned off.

Thus, the state of the selected cell along the bit line BL is used to set the value on the node SEN, from where it is transferred to the FLG node. At this point, the SEL 609 device can be turned on to transfer the value of FLG out to SBUS. Note also that once the result has been transferred from the SEN node on to the FLG node, the device FCO 611 can be used to isolate the rest of the sense amp circuitry from the latch 601, while still allowing the value latched on the FLG node to be transferred out through SEL 609. Consequently, the data latched on the FLG node can be scanned at the same time that the sense amp moves on to a next process if this does require the latch FLAG 601.

Lockout Read/Program Verify Operation

A second mode of operation is a lockout read/program verify mode. Although a somewhat more involved process than the more common no-lockout read, lockout read will draw less current as once a cell generates a positive read result (FLG high), it is removed from further sensing. Note that this is a lockout from further sensing in a series of sensing operations, as opposed to a programming lockout. For example, in multi-state memory a sensing operation, whether for a data read, program-verify, or other reason, will often include a series of sense operation. Putting this in the context of the exemplary embodiment, a series of sense operations will include checking the memory cell's state against a number of reference parameter by, in this example, pre-charge the cell's bit line, applying a sensing voltage to the word line, and seeing if the bit line discharges through the cell. This is done for a series of increasing sensing voltages corresponding to differing states. However, if a cell conducts enough to discharge the bit line at, say, the second sensing voltage, repeating the process again at a third, higher sensing voltage will supply no additional information, but only serve to waste the current used for it and any subsequent sensings; hence, the read lockout.

During a first read cycle, the operation for the lockout is similar to no-lockout operation just discussed with respect to FIG. 13, except that where in FIG. 13 at (2) the bit line is pre-charged through the BLS-BLC-BLX path, now the BL pre-charges through the BLS-BLC-BLY-FLA path. Consequently, at the end of the first read pass, the level on the FLG node will either be VDDSA or ground, as described in the last section. The process for the second and subsequent read cycles is illustrated with respect to FIG. 14. The second pass (and any subsequent passes) again begins with the H00 639 and FCO 611 devices turning on to pass FLG's voltage (either VDDSA or ground) to the SEN node, as shown at (1).

The set of sub-processes are marked as (2), where, if negative sensing is being performed, CLK will pre-charge to a certain level (for example, this could be 0.6V to 1.7V in a practical implementation), while if positive sensing, CLK will stay at ground. At the same time, the BLY 627 and STRO 637 devices turn on to pre-charge the bit line (BL). Seaming data from FLG to external data latch (such as 430-i, FIG. 11) can happen at the same time (also shown as (2)). This is due to the switch FCO 611 that can isolate the FLG node from the MUX node. Note that the level on the node FLG controls the device 613 above FLA 615. If the original FLG data is low, the bit line recovers through the BLS-BLC-BLY-FLA path as 613 is on. Otherwise, the bit line is held at the CLK level through the SEN-STRO-BLY-BLC-BLS path.

After the BL recovers, the STRO 637 device is turned off, then CLK is pulled down to the ground. At (4), the SEN node is pre-charged through the H00 639-FLA 615 devices. The CLK level then raises up, after which the XX0 633 device is turned on. The SEN node will develop, as shown at (5). If the memory cell is conductive, the SEN node will be discharged; otherwise the SEN node will not discharge much. After the SEN node develops, the memory turns off the XX0 633 device, then pulls down the CLK node to ground. The BLY 627 device is turned off. The FRB 605 device is then turned off and the RST 607 device turned on to reset the FLG node to VDDSA voltage level, (8). The FRB 605 device can then be turned on and the RST 607 device turned off. The MUX node is then pre-charged from the FLG node by turning on the FCO 611 device. As shown at (10), the STF 603 device is turned off, then the STRO 637 device is turned on to develop the FLG node based on the value at SEN, which is connected to the control gate of 635. After that, memory turns off the STRO 637 device, and then turns on the STF 603 device. Once the FLG level is developed, it can then be scanned out to SBUS through SEL 609.

Quick Pass Write, Two Forced Bit Line Values

During a program operation, for cells to be programmed the bit line is biased to a low voltage (typically ground), while cells that are not to be programmed or have verified and need to be locked out from further programming have their bit line biased high. In a quick pass write (QPW) arrangement, cells that are selected for programming that are approaching their target level are partially inhibited to slow the programming process for better accuracy by raising their bit line levels to an intermediate value. These bit lines values can be set in several ways. In this section the case where two of these bit line values are forced (or “2BL forcing”), both the program enable value (0V) and the QPW partial inhibit value (˜0.7V) are forced, while for the program inhibit case the bit line is left to float after being initially set high. An alternate arrangement where the high, program inhibit value is also forced (or “3BL forcing”) is considered in the next section.

Considering the process as shown in FIG. 15, at (1) data is set on the FLG node from the SBUS by way of the SEL device 609. If the bit line is inhibited, the corresponding FLG=VDDSA is set, while otherwise FLG=ground. The level on the FLG node then is used to set bit line value in (2): the BLS 623, BLC 621, BLY 627 and the FCO 611 node are raised to a high voltage. Then the bit line will either pre-charge to the VDDSA level or stay at ground, depending on its FLG data. At (3), the BLC 621/BLY 627/FCO 611 devices are turned off and the data is set again on the FLG node. If the bit line is inhibited/QPW, the corresponding FLG value is VDDSA, otherwise FLG=ground.

At (4), the BLC 621/BLY 627 nodes are then raised again to a high voltage. The memory will raise the FCO 611 device's gate node to a voltage level that will be used to control the QPW BL's voltage level, say ˜0.7V (for a VDDSA of ˜2.5V), for example, to set a level of ˜0.7V on BL. The inhibited bit line will float at a level high enough to inhibit the programming. The QPW BL is pre-charged through the FCO-BLY-BLC-BLS path, the programmed BL shares the same path but biased at ground by its FLG node. Once the bit line becomes stable at the appropriate level, programming can be done.

Quick Pass Write, Three Forced Bit Line Values

As just noted, for the “2BL-forcing” arrangement, the inhibited bit line will float. This section considers a mode where the inhibit value is also forced to the high supply level in a “3BL-forcing” arrangement, allowing all three values to be set by the single latch. The process, as illustrated with respect to FIG. 16, again begins with setting data on the FLG node from the SBUS by way of SEL 609, as shown at (1). If the bit line is inhibited, the corresponding FLG=VDDSA, otherwise FLG=ground. At (2), the H00 639 and FCO 611 gate nodes are raised to a high voltage, passing FLG's voltage level to the SEN node. The H00 639 device is then turned off.

Next, as shown by the paths (3), the memory raises the BLS 623, BLC 621 and BLY 627 gate nodes to a high voltage. The FCO 611 gate node is still kept at a high level from the previous sub-operation, (2). Based on these levels, the BL node will either pre-charge to the high VDDSA level or stay at ground, depending on its FLG data. The H00 639 gate node is biased at a threshold voltage that will keep the H00 639 device weakly on for the BL that is not to be inhibited; for an inhibited BL, the H00 639 device is still off as the MUX node is at VDDSA level. At the same time CLK node is charged to the VDDSA level. The inhibited BL is then pre-charged through the FCO-BLY-BLC-BLS path. The other BLs also share this path, but held at ground by the FLG node.

After some time, the STRO 637 device is turned on. The SEN node will still be a high level for the inhibited bit line, while it is at ground for the other cases. Consequently, the device 635 will also be on for the inhibited case. Consequently, as shown by the path (4), for an inhibited BL, its MUX node is hold firmly at VDDSA by the high CLK value. Consequently, the internal node SEN is again being used as an internal dynamic latch where a voltage level can be parked.

The BLC 621/BLY 627/FCO 611 devices are then turned off and the memory again sets data on the FLG node, as shown at (5). If BL is inhibited/QPW, the corresponding FLG=VDDSA, otherwise FLG=ground. The BLC 621/BLY 627 nodes are then raised to a high voltage again. For the FCO 611 device's node, this is raised to a voltage level that will be used to control the QPW BL's voltage level. The inhibited BL is held at VDDSA level through the CLK-SEN-STRO-BLY-BLC-BLS level. The QPW BL is pre-charged through the FCO-BLY-BLC-BLS path. Both paths are marked (6). The programmed BL shares the same path, but is biased at ground by its FLG node. After the bit line is allowed stabilize, the corresponding selected word line can be programmed.

Floating Quick Pass Write

The mode discussed in this section is another variation on the quick pass write technique, a Floating Quick Pass Write (FQPW) or Nakamura operation. The ability to perform this operation for a given bit line with only a single latch using the sense amp circuit of FIG. 12 will be discussed with respect to FIG. 17. In this variation on quick pass write implementation, the bit lines are again of three groups: a first group to be inhibited; a second group to be programmed; and the third group to be slow programmed. In a first step, the first group is taken to a value offset some below the high level, VDDSA−ΔV, where the offset can be a settable parameter. For example, if VDDSA=˜2.5V and ΔV is ˜0.7V, this would be ˜1.8V. The second group pre-charged, then left to float at 0V. The third group is set to a low value, say ˜0.7V, then left to float. At the second step (see (6) below), the first group is taken to the high level, while the bit lines of groups 2 and 3 will get coupled up if the bit line is adjacent to a bit line of group 1.

Referring now to FIG. 17, as shown at (1), the memory sets data on the FLG node: If BL is inhibited, the corresponding FLG value is VDDSA, otherwise FLG=ground. Next, as shown at (2), the H00 639 and FCO 611 nodes are raised to a high voltage to pass the FLG's voltage level to the SEN node. The BLS 623 device could turn on at this time. At (3), the H00 639 node's voltage is lowered to make it barely above a threshold voltage to keep H00 639 NMOS weakly on for the BL that is not inhibited; for an inhibited BL, the H00 639 device is still off since the MUX node is at VDDSA level. The CLK node is raised to a level lower than VDDSA by a certain amount (VDDSA−DELTA), corresponding to the group 1, step 1 described in the last paragraph. After some time, the memory turns off the H00 639 and FCO 611 devices completely. Note that at this point that the SEN node for inhibited BL case will be at a very high level, while it is at ground for other BL cases.

Once the BLC 621/BLY 627/FCO 611 devices are off, the memory again sets data on the FLG node at (4). If the BL is inhibited/QPW, the corresponding FLG level is VDDSA, otherwise FLG=ground. Once data is again set, the BLC 621/BLY 627/STRO 637 nodes are raised to a high voltage. The memory will raise the FCO 615 device's gate node to a voltage level that will be used to control the QPW BL's voltage level. The inhibited BL is charged through the CLK-SEN-STRO-BLY-BLC-BLS path, while. the QPW BL is pre-charged through the FCO-BLY-BLC-BLS path, and the programmed BL shares the same path but biased at ground by its FLG node. These paths are shown at (5). After some time, the memory turns off the FCO 611 device and raises CLK to the VDDSA level, as shown at (6). After the bit line stabilizes, the corresponding word line can be programmed.

Measurement of Cell Current Using External Bias Voltage

A final example is a mode allowing a cell's current to be measured using an external bias voltage. This is illustrated with respect to FIG. 18. Referring back to FIG. 12 first, the arrangement of the FLAG reset switch RST 607 allows for the INV node to be held to ground. By placing an external voltage onto a pad of the memory chip that can be connected to the SBUS node, this allows the amount of current drawn by the bit line to be measured. This can be used, for example, as part of a test mode to analyze device characteristics. When measuring the cell current, for example, half of the bit lines could be selected, the other half unselected. (In the following, it is assumed that the unselected BLs are also biased.)

For the selected BLs, the RST 607 device is always on to pull its INV node to the ground as shown at (1), its STF 603/FLA 615 devices are off, and its FCO 611 device is on. For an unselected BL, its RST 607 device is off, while its STF 603/FLA 615 device is on, its FCO 611 device is off. For the unselected BL, its FLG node is initialized to be at ground. Note that at this point that the FLG node of the selected BL is not controlled by the FLAG latch anymore, which is now floating at this point.

Next, the SEL/BLY 627/BLC 621/BLS 623 devices are turned on. BLY 627 and BLS 623 are at a high voltage. For a selected BL, its BLC 621 node is at a very high voltage to pass the bias voltage from the external pin to the BL through the SBUS-SEL-FCO-BLY-BLC-BLS path. For the unselected BL, its BLC 621 node is biased at a level to control the BL's voltage, the unselected BL are pre-charged through the FLA-BLY-BLC-BLS path. These are both shown at (2). The amount of current being drawn can then be measured.

Second Embodiment

The preceding discussion, which are developed further in U.S. patent application Ser. Nos. 13/277,915 and 13/277,966, was based on the circuit of FIG. 12. This section presents another embodiment, shown FIG. 19, which a variation of the circuit of FIG. 12 and is numbered similarly (i.e., 701 of FIG. 19 corresponds to 601 of FIG. 12).

Relative to the circuit of FIG. 12, the embodiment of FIG. 19 now includes the transistor ICO 791 connected between the INV node of the latch 701 and the MUX node. This can remove the need for a dynamic latch operation. INV has the polarity of the program or verify operation and, as discussed below, during binary (SLC) programming, ICO 791 can pass the VDDSA level to the bit line BL for erase or verify pass of a selected cell along the bit line and pass VSS to BL for programming of the cell.

The circuit of FIG. 19 also differs from that of FIG. 12 in that the drain side of H00 739 is now connected to high voltage level rather than MUX, so that the SEN precharge is no longer related to FLG. As will be discussed below, this allows the XX0 733 assist to be done at the same time SEN is precharged. In addition, FLG can be reset to VDDSA in parallel with SEN precharging. With these modification, the programming time for both SLC and MLC operations can be improved by severel percent.

The operation of the circuit of FIG. 19 during a binary, or SLC, program operation can be illustrated with respect to FIGS. 20A and 20B, where FIG. 20A shows the operation for the circuit of FIG. 12 and FIG. 20B shows the same case for FIG. 19. Considering the case of a “Fast SLC” program operation, the FLG value in 601 or 701 is not reset by transferring data between it and the latches outside of the sense amp in order to thereby speed up programming and the sense amp can keep the original program data with adding additional latch. Before the first program pulse, the memory transfers in the data into the sense amp. As discussed in more detail above, for a program cell FLG=VDD and for the erase cell FLG=VDD. During verify, FLG is flip from VDD to VSS though the STRO 637 and SEN 635 path (CLK=VSS during strobe) for the cell that passes verify.

For the circuit of FIG. 12, in order to inhibit the cell from programming, the circuit biases the bit line BL to the VDD level for preparing boosting at the later stages. Since FLG=VSS for the erase cell or verify pass cell, the FLA 615 path is used to pass VDDSA. When the memory is to program the cell, it will keep the BL to VSS level. In order to do so, the FLG level is first transferred to the SEN node (SEN=VDD for the program cell, and VSS for the erase or verify pass cell), and then the STRO 637 path is used to discharge BL to VSS (CLK=VSS). FIG. 20A is the timing diagram of this operation: initally H00 and FCO are taken high to pass the value to set the value on SEN, after which the STRO value goes high. (See discussion in preceeding sections for more detail.)

To speed up this operation, the embodiment of the circuit of FIG. 19 adds the transistor ICO 791 to provide a path between the INV node of the latch circuit FLAG 701 and the MUX node. This allows the memory to skip the “dynamic latch” operation (that is, remove FLG to SEN transfer) of the circuit of FIG. 12 at the beginning of FIG. 20A, thereby speeding up the operation. The corresponding operation of FIG. 19 is illustrated by the waveforms of FIG. 20B. In contrast to FIG. 20A, in FIG. 2011 both the H00 and FCO levels stay low, thereby saving the time to raise these values, perform the FLG to SEN transfer, and take these values back down. In FIG. 20B, the STRO value also can stay low as the SEN value no longer needs to be sifted to the BL, as this can be done by the ICO path.

The design of FIG. 19 also allows for the verify operation to be improved with respect to that of FIG. 12. FIGS. 21A and 21B respectively illustrate waveforms for an SLC program verify operation using the circuits of FIGS. 12 and 19.

Considering FIG. 21A first, this shows the waveforms for the SLC program verify for the circuit FIG. 12, as is described further in the corresponding section above. This process has the SEN node pre-charged based upon the FLG value, for which H00 639 and FCO 611 are high. During SEN precharge, the memory has to disable XX0 633 to avoid a direct path current from VDD (BLX 625)→COM (XX0 633)→SEN (H00 639)→MUX (FLG=VSS). Consequently, as shown in FIG. 21A, the XX0 value needs to stay low while H00 is high, without any overlap. (In FIGS. 21A and 21B, the intermediate value of XX0 before it goes fully high is an optional variation, as opposed to keeping it low until taken to its full value.)

In FIG. 19, as H00 739 is now connected between SEN and VDD, rather than MUX, the SEN node can be directly connected to VDD as needed; and, as this cuts of the path between MUX and COM by H00 739 and XX0 733, the high H00 and XX0 values can overlap. This is shown in FIG. 21B, where the hump in the H00 no longer needs to be back to the low voltage level before XX0 can be raised, thereby speeding up operation. The combined changes of FIGS. 20B and 21B can allow an increase of around 5-10 percent in SLC programming performance.

The change in the connection of H00 739 in FIG. 19 relative to H00 639 in FIG. 12 can be used to improve multi-state programming performance. FIGS. 22A and 22B respectively show a MLC program verify operation for the circuits of FIGS. 12 and 19. In the MLC program verify operation using FIG. 12, as illustrated in FIG. 22A (and as described in more detail above), the FLA 615 path is used to pre-charge SEN node. The memory also will need to reset FLG from VSS to VDD before strobing, which cannot be done in FIG. 12 until the pre-charge of the SEN is done. (In FIGS. 22A and 22B the four bumps of the RST signal correspond to the four states in a 2-bit per cell embodiment.)

In the embodiment of FIG. 19, H00 739 can be used to connect the SEN node to VDDSA. This allows the SEN node to be pre-charged without using the FLA 715 path, which in turn allows the SEN pre-charge to be done concurrently with resetting the FLG level. In FIG. 22B, the XX0, H00, and CLK lines are much as before to pre-charge SEN. However, now the RST waveform to reset FLG can now be moved forward to overlap with pre-charge of SEN, along with FRB, the rising of FLA, and the rising FCO all being shifted earlier. This allows the MLC verify to be sped up, improving MLC programming performance by several percent.

Third Embodiment

FIG. 23 is a third embodiment of a sense amplified circuit that can achieve faster access time with smaller layout area and less power consumption. In FIG. 23, corresponding elements are numbered similarly to the embodiments of FIGS. 12 and 19, (i.e., FCO is 611, 711 and 811 in the corresponding figures). Relative to the embodiment of FIG. 19, the elements of FLAG 801, ICO 891, and FCO 811 are reversed.

A first difference relates to the power supply connections of the sense amp. To reduce power consumption, the embodiment of this section separates the power supply level of the latch 801 and the power supply level used to drive the bit lines. When in read and verify mode, the sense uses one supply level, such as of 2.5V or more, to drive a bit line. However, there is usually no reason to use such high voltage for data storage and program inhibit operations. For example, a typical program inhibit level requirement for a bit line BL is lower, around 1.8V to 2.0V. In this embodiment, another separate power supply is used for this function, resulting in lower charge consumption during program. Also, because the latch supply level is being reduced, the average current drawn for scan operation and strobe operation is reduced.

This is shown in FIG. 23, where these function are split by having the sense amp connected to the two different supply levels. The level VDD, which is used for the program inhibit, is used at the supply level at the latch FLAG 801, rather than the VDDSA level as in FIG. 19. Outside to the latch, the higher VDDSA level is still connected through BLX 825 and HLL 839 for use in pre-charging bit lines for sense operations. In the exemplary embodiment, VDD is available on the chip as it is used by various peripheral circuit elements and the VDDSA level can also be provided as a regulated level with use of a charge pump.

Another difference from the embodiment of FIG. 19 is that FIG. 23 lacks the elements corresponding to the PMOS transistors 713 and FLA 715, so that the circuit requires less area. The program inhibit level bit line level can be pre charged directly from the INV latch level. As shown in FIG. 23, the only PMOS transistors are RSTF 803 and RSTI 805 of the latch circuit, which are connected only to VDD. As VDD is the common supply level used in the other peripheral logic circuitry on the device, there is no longer a need for two separate NWELLs, one for VDD and one for VDDSA. This can help to minimize the layout area in peripheral circuitry and local buffer area. Use of the lower VDD level in the latch can also help reduce the amount current, and therefore power consumed, in the operation of the FLAG latch 801.

Another difference between FIGS. 19 and 23 is that the reset transistor RST 707 is missing in FIG. 23, which has instead added the switch MTG 893. MTG 893 can discharge the latch node INV (through ICO 891) and also discharge the latch node FLG (though FCO 811). The MTG transistor 893 can also discharge bit line without using latch information. This arrangement allows the circuit to perform operations in parallel, discharging the bit line at the same time as transfers the sensing result out to other latches.

The embodiment of FIG. 23 further differs from the preceding embodiment in the connected in its “strobing” path, the path through STRO 837 from the CLK node to the FLG node of the latch 801. In FIG. 23 this path is connected to the latch node FLG directly at the node marked X above FCO 811, instead of being connected at the MUX node as in FIG. 19. This direct connection removes the need for a pre-charge sequence of the MUX node in order to avoid charge sharing during strobe, when the analog voltage on the SEN node is converted to a digital value (VDDSA or ground/VSS) at FLG.

Fourth Embodiment Hybrid Lockout

This section presents a fourth set of sense amp embodiments that add several features to the embodiments of the preceding section. In particular, it includes some modifications adapted to the implementation of a quick pass write (QPW) functionality and a “hybrid” lockout sensing operation, which is described below. FIG. 24 shows an exemplary circuit for the fourth embodiment. In FIG. 24, corresponding elements are again numbered similarly to the embodiments of FIGS. 12, 19, and 23, (i.e., FCO is 611, 711, 811, and 911 in the corresponding figures).

Much of FIG. 24 is much as shown in FIG. 23 and will function as described in the preceding section. A first difference of FIG. 24 relative to FIG. 23 that although the nodes COM and SEN can both be connected to VDDSA through respective switches BLX 925 and HLL 939, this is now done by way of switch 941 whose gate is connected to FLG. A switch 943, also controller by FLG, is also now connected between COM and SEN in series with XX0 933. When FLG is high, SEN and COM can both be connected to VDDSA and to each other, but when FLG is low, these paths are now cut off. When FLG is low, INV is high and a newly added path to COM is available: COM is now connected to a node to receive the level SRCGND by way switch GRS 947 in parallel with switch 945, whose gate is connected to INV.

FIG. 24 now also includes a second latch circuit LATCH 951 connected to the SEN node. LATCH is also connected to the bus SBUS through switch 961 controlled by SEL. To be able to selectively connect either FLAG 901 or LATCH 951 to SBUS, a switch SCNL 963 is connected in series with 961 and a switch SCNF 965 is added in parallel with 909. LATCH 951 can either be implemented as a static or dynamic latch, where a dynamic latch is shown in this example. The node LAT is connected to ground by way of a switch STRL 955 in series with switch 953, whose gate is connected to the node SEN. LAT can also be connected to VDDSA by switch PCHL 957 and a capacitor CLAT 952 is connected between LAT and ground to hold charge for the node LAT. The level on LAT is then connected to the control gate for the switch 959.

As with the embodiment of FIG. 23, two different supply levels are again used in the sense amp circuit of FIG. 24, where most of the circuit again using VDDSA, while the latch FLG 901 uses a different level. In the embodiment of this section, as shown in FIG. 24, though, the latch FLG uses a higher voltage level that can be supplied from a charge pump. In FIG. 24, this voltage level in labeled as VFOUR as this example uses a value of 4V, although other values can be used. In this example, the VDDSA level can be taken as ˜2.5V and the level at the SRCGND node can range up 1V-1.7V or even 2V. For these values, the use of a higher (here 4V) power supply for FLAG 801 also for the circuit to easily to pass the (e.g. 2V) SRCGND or the (e.g. 2.5V) VDDSA to the BL node while only using NMOS devices. Here, when FLG is high (and INV low), the switches 841 and 843 allow the VDDSA level to pass due to the higher VFOUR value at their gate, while when INV is high (and FLG low) the switch allows a wide range of SRCGND values to pass. In this arrangement, VDDSA is the level used for both to pre-charge for sensing and for program inhibit. For quick pass write (QPW), the supply is also from VDDSA, but the level is clamped by the BLC 921 gate voltage. SRCGND is the path for verify lockout or to program BL (VSS). Also, by restricting the higher VFOUR value to just FLAG 901, it keeps the sense amp from drawing too much current as would result from also setting VDDSA at this higher value.

The use of this higher voltage (here 4V) for the FLG and INV values of the latch FLAG latch 901 allows the switches 841, 843 and 845 to pass the full range of VDDSA and SRCGND values used in the sense amp to be passed on to the bit line at BL while using only NMOS devices in the paths. This allows for the sense amp of FIG. 24 only use N-type devices, except for the latch FLAG 901, and still set all of the desired values for hybrid lockout sensing operations. Without this higher VFOUR value, in order to pass a higher voltage than something like 1.2V from SRCGND to lockout the bit line at BL, previous desings would use a CMOS pass gate to pass this level to BL. And also in order to resolving the clocking noise issue, a CMOS pass gate may also be added in between SEN and BL. However, the use of CMOS pass gates, where an NMOS and a PMOS are connected in parallel, has some disadvatages. One of these is that there can be a forbidden region of a range between where the NMOS and PMOS conduct, so that some levels will not be passed. Another is the increased area and metal routing that PMOS devices need, particularly if they require a separate well level from the PMOS devices in FLAG. By using only NMOS devices for the analog path, the embodiment of FIG. 24 can resolve the limited CMOS operation zone issue also achieve a compact layout area.

As noted above, the addition of the second latch LATCH 951 allows the sense amp of FIG. 24 to support a “hybrid lockout” mode for sensing. Both Quick Pass Write (QPW) and lock-out sensing have been discussed above with respect to the first set of embodiments. Hybrid lockout sensing is a mixture of these ideas, in that the bit line is locked out after verify at the high verify level of a state, but not locked out between verifying at the low and high verify levels of a state; that is, bit lines are locked out between different states, but not between the low and high verify levels of each state. This hybrid mode can provide no-lockout verify programming performance with lockout program current level.

FIG. 25A illustrates a typical set of word line waveforms for a comment implementation of quick pass write (QPW) and FIG. 25B illustrates an alternate approach that is preferable used with the sense amp arrangement of this section. FIG. 25A is a schematic illustration of a QPW verify control gate waveform. Here, the memory cells can be program from a ground or erased state into states A, B, C, and so on. After a programming pulse, each cell is verified for the different levels and, if the cell verifies at its target level, it is inhibited from further programming. In a QPW program, each verify level is split in two: a low verify and a high verify. For example, the A state is now verified for the low level VAL and high level VAH, and similarly for the other states. When a cell verifies at the high level for its target state, it is fully inhibited, while if it verifies at the low level of its target state it is partially inhibited to slow, but not stop programming. (For more discussion of the quick pass write concept, see U.S. Pat. No. 7,345,928.)

The approach of FIG. 25B shows a slightly different approach. (In FIGS. 25A and 25B the time scales are not meant to correspond, being schematic in both cases.) In a sense operation with the sense amp of FIG. 24, a bit line is pre-charged, a sensing voltage placed on its control gate and then after a period of time, the amount of discharged is checked. In the arrangement of FIG. 25B, only one control gate voltage (VCG) is used for each state, so that, for example, VA in FIG. 25B would correspond to the high level VAH of FIG. 25A and similarly for other states; but now, for each level, the discharge level is checked twice in relatively quick succession. These two sense operations then correspond to the low and high levels, hence the notation ˜VAL, ˜VAH, and so on. The bottom line shows the strobe waveform as applied to STRO 937. This first time STRO goes high is to set the QPW latch LATCH 951 and the second time to set FLAG 901, both being done from the same discharge: When STRO is high, the circuit latches in the sensing result into the FLG node; STRL also has the same polarity as STRO and when it is high, the sensing result would be latched into node LAT. (More detail on implementing a quick pass write operation using this sort of sensing technique is given in U.S. Pat. No. 8,233,324.) Lockout sensing is only implemented by the FLG/INV value, while LAT is to set partial programming inhibit.

Under this arrangement, when the sense amp has FLG is high (INV low) for sensing. When FLG is low (INV high), sensing is locked out and the SRCGND level can be connected to the BL node for verify lock out. In this way, the FLG value drives bit line and only flips when go A→B, B→C, etc., while LAT is independent of BL driving current and can be used for the QPW value.

Consequently, the fourth set of embodiments described in this section has a number of features that be advantageously applied in the sense amp's operation. A first of these is the use of separate power supply levels for the primary data latch and the bit line driving path. In particular, the primary latch uses a higher power supply level, such as can be provided by a charge pump. Another feature is the use of only NMOS devices only for the analog path, which can not only resolve the limited operation zone issue that can arise from CMOS pass gates and also achieve a compact layout area. Further, the addition of a latch allows the sense amp to support a “hybrid lockout” mode for balancing performance and current consumption.

Cell Current Control Through Power Supply

Power consumption is one of the major concerns in memory devices. In sense amp circuits, such those described above, a significant amount of the device's current consumption is the cell current flowing from the sense amps into the bit lines. The amount of cell current changes over time, typically decreasing as the number of write/erase cycles increases. In arrangement like those illustrated above, the amount of bit line current depends on the bias level of a clamp circuit, such BLC 821 in FIG. 23. To ensure proper operation over the life of the device, a bias voltage for the bit line current is set to meet the end of life W/E cycle; however, this same potential will results with much high power consumption at fresh unit.

As the bit line current supplied to the memory cells is similar to the current of the supply level (such as VDDSA or VDD) for the sense amps, the sensing of the current through the supply generator can be used to adjust this bias level and the consequently cell current.

The situation can be illustrated with respect to FIG. 26. At top is the current level Icell as a function of write/erase W/E cycle. If the bit line clamp voltage VBLC is kept a constant level, the Icell behavior is as shown at 1001, where here VBLC is chosen so that Icell remains at least at a level Icell₀ for at least a number of W/E cycles x₀. When the device is fresh, this means it will draw much more current than is needed. If instead the VBLC level is stepped as the device ages as shown in the lower part of FIG. 26 at 1005, the current can be kept above, but closer to, Icell₀, as shown at 1003. This keeps the Icell in the needed range while reducing current usage. One way to do this would be to base VBLC directly upon the “hot count” or “experience count”, but this is not easily done in practice due to device variations. Instead, the approach here is to monitor the Icell level through the supply level, and adjust the VBLC value accordingly.

FIG. 27 is a block diagram illustrating some aspects of an exemplary embodiment for effecting this. The current Icell is flowing through the NAND strings 1011 to the common source line CELSRC or VSS (ground). (For more detail on setting the CELSRC level, see U.S. Pat. No. 7,764,547 or U.S. patent application Ser. Nos. 13/945,117 and 14/175,196.) Each of the bit lines connected to the NAND strings will be supplied through a corresponding clamp circuit of transistor BLC 821 whose gate is set at VBLC. Here BLC 821 can correspond to the element BLC 821 of FIG. 23 or the corresponding element in the other embodiments presented above. The other elements of the sense amp circuits are suppressed to simplify the discussion here, but each selected bit line would have a corresponding sense amp as represented by the clamp BLC 821. (In the exemplary embodiment, Icell is the combined current for all of the NAND strings of an array or portions of an array sharing a common source line, but in other embodiments it can be for a finer structure, even down to the individual NAND strings.)

The power supply of VDD or (here) VDDSA for the sense amps is provided are supplied by a power transistor 1023 whose gate is controlled by the output of the op amp 1021. FIG. 27 shows a simple embodiment for this and other arrangements can be used. In a typically arrangement, there will multiple such individual elements supplying the sense amps, but these will be common to all (or at least multiple ones) of the sense amps. The power transistor is connected between an external supply level VEXT and the supply node of VDDSA for the sense amps. The control gate of 1023 receives the voltage PG generated from compared 1021 that has inputs a reference voltage VREF and feedback of VDDSA from a voltage divider. The current through transistor 1023 is IVDDSA. The power supply, VDDSA, supplies bit lines for both negative and positive sensing with positive and negative word line levels. Assuming the current is stable, then IVDDSA˜ICELL (assuming the current used by the regulation circuitry is such that IVDDSAREG<<ICELL).

The level PG is also used to control a second transistor 1025 that is connected between VEXT and, though a current source iCELL_target 1029, ground. The transistors 1025 and 1023 are sized with a 1 to N ratio as 1025 is not used as a supply, but only for current determination purposes and can be sized much smaller. The level on a node between 1025 and 1029 will then reflect the amount of current ICELL flowing from the supply relative to the level of the current source. A comparator 1027 then has one input connected to this node and the other input connected to a reference level VREF′, which may or may not be the same as VREF depending on the implementation. The output of 1027 of then used by the logic circuitry/bit line driver (BLDR) 1031 to set VBLC. Given the transistor sizing of the VDDSA supply, a ratio can be determined to set the target cell current. Once compared, a feedback can be provided to set BLC voltages to control cell current from the beginning to the end of life for the device.

The setting of the VBLC can be done as various times, depending to the implementation: periodically as the device ages; before an operation (such as a read or write); or by monitoring the current level during the course of an operation. For example, at beginning of a multistate read or write, the VBLC level to be using during the operation can be determined just before beginning operation, so that in, say, a write operation it be done prior to the lower page program to set the VBLC levels to be used over the course of writing the lower and any upper pages. In other embodiments, the level can be varied up and down during the course of a sensing operation, such as when bit lines are locked out and less current is needed, or when, during a no-lockout read, as the current increases as more and more bit lines become conducting as read voltages increase.

FIG. 28 is box diagram of the elements of the process and associated circuitry of the logic/BLDR block 1031 of FIG. 26 for an exemplary embodiment. FIG. 28 again includes the comparator 1029 that provides a measure of the iVDDSA/iCELL level relative the reference level VREF′. The ICELL measurement can be converted into a digital value at the A/D converter 1041 as, for example, a 2-bit value (as in FIG. 26) which can then be stored into a register at 1043. When the VBLC setting process is enabled, the flag is then fetched at 1045 and used to offset a default VBLC value by the specified number of steps at 1047. This value is then supplied to the bit line driver BLDR 1049 to set the gate level on BLC 821. The default value for VBLC can either be a lower, fresh device value that is then incremented up as needed based upon the ICELL value; a higher, aged device value that is incremented downward; or an intermediate level. (In any of the cases, the default value can be established during device characterization.) For example, in a process that can be automatically enabled at the beginning of a program operation, the ICELL is measured using the fresh VBLC level. The VBLC level can then be increased a step at a time until the input at the comparator meets the reference level, at which time the VBLC level for the operation can be set.

The techniques of this section can be used for any sort of sensing operation and also can reduce device variation since the levels are replicated locally at the generator. Although the exemplary embodiment of FIG. 27 uses a feedback type of arrangement for setting the level on BLC 821 based on the current flowing through it, the current detection portion of FIG. 27 (that is, without BLC 821, the NAND string 1011, and the source line 1013) can be used more generally to determine the current level iVDDSA or iCELL. In particular, the output of the comparator 1029 (either before, after on in some intermediate stage of the logic of 1031) can be used to give an indication of the current level, whether or not it is used to control a clamp such as BLC 821.

Conclusion

Although the various aspects of the present invention have been described with respect to certain embodiments, it is understood that the invention is entitled to protection within the full scope of the appended claims. 

It is claimed:
 1. A non-volatile memory circuit, comprising: an array of non-volatile memory cells; a plurality of bit lines connectable to the memory cells; regulation circuitry connectable to receive an external power supply level and provide therefrom a regulated voltage level; a plurality of sense amps, each with a clamp transistor through which the regulated voltage level is connectable to supply a selected bit line; and current control circuitry connected to the regulation circuitry to perform a comparison of the amount of current supplied by the regulation circuitry to the bit lines with a reference level and connected to the control gates of the clamp transistors to supply a clamp voltage thereto based upon said comparison.
 2. The non-volatile memory circuit of claim 1, wherein the current control circuitry comprises: a first transistor and a reference current source connected in series between the external power supply level and ground, wherein the gate of the first transistor is connected to the regulation circuitry to receive a voltage indicative of the amount of current supplied by the regulation circuitry to the bit lines; a comparator having a first input connected to a node between the first transistor and the reference current source, having a second input connected to a reference level; and logic circuitry connected to receive the output of the comparator and determine therefrom the clamp voltage and connected to the control gates of the clamp transistors to supply thereto the clamp voltage.
 3. The non-volatile memory circuit of claim 2, wherein the regulation circuitry includes one or more second transistor through which is supplied to the bit lines, and wherein the voltage indicative of the amount of current supplied by the regulation circuitry to the bit lines is a control gate voltage for one or more of the second transistors.
 4. The non-volatile memory circuit of claim 3, wherein the first transistor is sized smaller than the second transistors.
 5. The non-volatile memory circuit of claim 2, wherein the logic circuitry includes an analog to digital converter connected to receive the output of the comparator generate therefrom a multi-bit digital values.
 6. The non-volatile memory circuit of claim 5, wherein the logic circuit offsets the clamp voltage relative to an initial clamp voltage based upon the digital value.
 7. The non-volatile memory circuit of claim 6, wherein the initial clamp voltage is determined based on device characterizations for fresh devices.
 8. The non-volatile memory circuit of claim 1, wherein the current control circuitry is enabled to supply the clamp voltage during sensing operations.
 9. The non-volatile memory circuit of claim 8, wherein the sensing operations include data verify operations.
 10. The non-volatile memory circuit of claim 8, wherein the sensing operations include data read operations.
 11. The non-volatile memory circuit of claim 8, wherein the current control circuitry performs the comparison of the amount of current supplied by the regulation circuitry to the bit lines with a reference level as an initial phase of a data write operation.
 12. The non-volatile memory circuit of claim 1, wherein the array of non-volatile memory cells is formed according to a NAND type architecture.
 13. The non-volatile memory circuit of claim 1, wherein the memory device is formed as a monolithic three-dimensional semiconductor memory device.
 14. The non-volatile memory circuit of claim 13, wherein the monolithic three-dimensional semiconductor memory device has a plurality of memory device levels vertically disposed above a silicon substrate wherein said memory device levels have a plurality of the memory cells, each of which comprise a charge storage medium with the corresponding control gate horizontally disposed relative to said charge storage medium, wherein the memory cells in a memory device level are horizontally separated from each other and arranged in two or more horizontal rows of two or more memory cells, at least one of said memory device levels having memory cells substantially vertically aligned with memory cells of a vertically adjacent memory device level, and at least one control gate being common among at least two memory cells in one of said horizontal rows in one of said memory device levels and among at least two memory cells in a second one of said horizontal rows in said one of said memory device levels.
 15. The non-volatile memory circuit of claim 1, wherein the regulated voltage level is used by the sense amps in pre-charging bit during sensing operations.
 16. The non-volatile memory circuit of claim 15, wherein the regulated voltage level is of a higher voltage than the on-chip high logic level.
 17. A non-volatile memory circuit, comprising: an array of non-volatile memory cells; a plurality of bit lines connectable to the memory cells; regulation circuitry connectable to receive an external power supply level and provide therefrom a regulated voltage level; intermediate circuitry through which the regulated voltage level is connectable to supply a plurality of selected bit lines; and current determination circuitry connected to the regulation circuitry to perform a comparison of the amount of current supplied by the regulation circuitry to the bit lines with a reference level comprising: a first transistor and a reference current source connected in series between the external power supply level and ground, wherein the gate of the first transistor is connected to the regulation circuitry to receive a voltage indicative of the amount of current supplied by the regulation circuitry to the bit lines; and a comparator having a first input connected to a node between the first transistor and the reference current source, having a second input connected to a reference level, and providing an output indicative of the amount of current being supplied to the selected bit lines by the regulation circuitry.
 18. The non-volatile memory circuit of claim 17, wherein the intermediate circuitry comprises: a plurality of sense amps, each with a clamp transistor through which the regulated voltage level is connectable to supply one of the selected bit lines.
 19. The non-volatile memory circuit of claim 18, further comprising: current control circuitry connected to receive the output of the comparator and connected to the control gates of the clamp transistors to supply a clamp voltage thereto based upon said output of the comparator.
 20. The non-volatile memory circuit of claim 17, wherein the memory device is formed as a monolithic three-dimensional semiconductor memory device.
 21. The non-volatile memory circuit of claim 20, wherein the monolithic three-dimensional semiconductor memory device has a plurality of memory device levels vertically disposed above a silicon substrate wherein said memory device levels have a plurality of the memory cells, each of which comprise a charge storage medium with the corresponding control gate horizontally disposed relative to said charge storage medium, wherein the memory cells in a memory device level are horizontally separated from each other and arranged in two or more horizontal rows of two or more memory cells, at least one of said memory device levels having memory cells substantially vertically aligned with memory cells of a vertically adjacent memory device level, and at least one control gate being common among at least two memory cells in one of said horizontal rows in one of said memory device levels and among at least two memory cells in a second one of said horizontal rows in said one of said memory device levels. 